FANCO-16 VERSION 4 THE LAYERED SOUND CHIP ====================== Prototype, October 2026 Version 4 is version 3 with a new sound chip and multitouch. Everything else (processor, screen, blitter, timer, images) is unchanged; see the v3 SPEC.txt. The v3 SID registers at 40-5F configure SIREN's factory sound setup. They are not plain memory or a second chip. The chip computes every unit on every sample, heard or not; synthesis cost is bounded. Registers are write-only from the chip's point of view: reading them gives back what you wrote, not the chip's state. All addresses are hexadecimal. MAP === 0040-005F SID factory façade (v3 SOUND.txt) 0400-07FF 32 operators, 32 bytes each 0800-087F 8 filters, 16 bytes each 0880 master volume, 0-255 0900-09FF 32 ramps, 8 bytes each 0A00-0AFF 8 delay lines, 32 bytes each 0B00-0B1F 2 capture channels, 16 bytes each 80-A7 Touch points (input, see the end) FACTORY SID CONFIGURATION ========================= On reset, operators 0-2 and filter 0 implement the v3 SID-inspired chip. Old writes keep the v3 PAL frequency scale, 12-bit pulse widths, gate/test, sync/ring, waveform combinations, AD/SR rates, filter routing and mode, voice-3 mute and 5B sine extension. Output is mono in both stereo channels with v3 gain/headroom. This preserves v3 behavior, not every analog quirk of an actual 6581/8580; see v3 SOUND.txt. These are SIREN operators and filter states, not a separately rendered legacy engine. Their outputs remain available to native modulation and capture. SID writes also configure native pitch, shape, envelope and routing targets; factory calculation retains exact v3 rates, including zero frequency, rather than rounding the sound to native pitch/time-code precision. The native target bytes are internal chip state, not a second set of writes into guest RAM. SID writes change only their corresponding pitch, pulse-width, waveform/gate, envelope, filter or master-volume settings. They do not reset native pan, sends, feedback, delay lines or extra operators. Native field writes select that field's native encoding, not another chip or an entire replacement voice configuration. For example, a pitch write preserves a custom native envelope; 57 changes filter routing, and 58 changes the shared master-volume target. Factory voices and filter output can feed the native delay bus through their send controls. RAM reads always return the bytes last written to that address, not the translated targets. Image startup retains the v3 .sound volume and explicit register segments. Plain zero RAM is not replayed over the factory configuration. Native applications should set master volume. No existing v3 game bytes or IDs are changed. COMPATIBILITY LIMITS ==================== The prototype's new map is NOT fully v3 RAM compatible. 0400-0BFF was usable v3 RAM: writes there now also configure sound (including reserved bytes). Image segments and loaded libraries there also configure sound. The worker writes touch input to 80-A7 each slice; v3's SPEC.txt reserves that range, rather than promising it as ordinary RAM. Programs using reserved bytes there may still conflict. This is the historical v4 register layout. V5 uses the agreed compact 0100 generator bank and 0200 mixing/effects bank; see v5/SOUND.txt. The old v4 native image is not automatically remapped into v5. Existing v3 bytes/IDs are not silently rewritten. PITCH ===== Pitches are 16-bit words on one scale: Hz = 440 * 2 ^ ((p - 8000) / 3072) 8000 is A4. 256 steps make a semitone, 3072 an octave. MIDI note n is n * 256 + 3B00, so the note number is simply the high byte plus 3B. 0000 is about 0.27 Hz (slow enough for LFOs). Pitches above 24 kHz are held at 24 kHz. The same scale sets filter cutoffs. A straight ramp on a pitch is a musical glide. OPERATORS ========= An operator is a phasor, a waveform, an envelope and one modulation input. Operator n starts at 0400 + n * 20. +00 word PITCH +02 byte WAVE 0 sine 1 triangle 2 saw 3 pulse 4 noise 5 constant 1 +03 byte GATE bit 0: gate. 0 to 1 starts the envelope, 1 to 0 releases it. Bit 1: also restart the phase at 0. +04 word SHAPE pulse: width (8000 = square). Noise: color, 0 white ... FFFF dark. +06 byte MOD bits 0-4: source operator, bits 5-7: mode 0 none 1 phase (FM) 2 ring / AM 3 sync 4 pitch (vibrato) 5 pulse width +07 byte DEPTH phase: source * DEPTH / 64 cycles. Ring: 255 is full ring, less mixes in AM. Pitch: source * DEPTH * 4 steps. Width: / 512. +08 byte LEVEL to the mixer, 0-255. A modulator can be 0. +09 byte PAN 0 left, 80 center, FF right +0A byte SEND to the delay bus +0B byte ROUTE 0 mixer, 1-8 into filter 1-8 (LEVEL is then the input gain). +0C 8 bytes envelope: level and time of segments 1-4 +14 byte ENVFLAGS bits 0-3: segment is exponential (else linear) bits 4-5: sustain segment bit 6: sustain on bit 7: loop while gated +15 byte FEEDBACK self phase modulation +16-1F reserved A modulator's output is its waveform times its envelope, before LEVEL. The source may be any operator; a higher-numbered one gives its value from the previous sample. Envelopes --------- A segment moves from the current level to its level (0-255) in its time. Time 0 is instant; otherwise 1 is 1 ms and every 16 doubles it (17 = 2 ms, 161 = 1 s, 255 = about 60 s). On gate on, segment 1 starts. After a segment: if sustain is on and this is the sustain segment, the level holds while gated. After segment 3 it loops back to 1 (loop bit) or holds. Gate off jumps to segment 4 from the current level. A usual ADSR: 1: 255, attack, linear 2: S, decay, exp 3: S, 0 4: 0, release, exp ENVFLAGS = 0A + 40 + 10 (sustain on, seg 2) FILTERS ======= State-variable filter n starts at 0800 + n * 10. +00 word CUTOFF on the pitch scale +02 byte RESONANCE 0-255 +03 byte MODE 1 lowpass, 2 bandpass, 4 highpass, added together; 0 passes the input through +04 byte LEVEL +05 PAN +06 SEND +07 byte MODSRC bit 7 on, bits 0-4 op +08 byte MODDEPTH cutoff + source * DEPTH * 48 steps An operator with wave 5 and level 0 makes an envelope that sweeps a filter. RAMPS ===== A ramp moves any chip register smoothly to a target. Ramp n starts at 0900 + n * 8. +00 word DEST register address (0400-0AFF) +02 word TARGET +04 word TIME in 16-sample units (1/3 ms) +06 byte MODE 1 linear, 2 exponential; bit 7: DEST is a byte, and the ramp's high byte is written there +07 reserved Writing MODE starts the ramp from the register's current value. The chip then writes DEST every sample until TARGET is reached. DELAY LINES =========== Each line holds 2^19 samples (10.9 s). Line n starts at 0A00 + n * 20. +00 byte INPUT gain from the delay bus +01 byte DAMP lowpass in the line, 0 off +02 byte MODE bit 0: allpass (tap 0 becomes a Schroeder allpass with gain APGAIN) +03 byte APGAIN signed, / 128 +04 12 bytes tap 0 +10 12 bytes tap 1 +1C-1F reserved Tap: +0 word POSITION, a 16-bit float: 4-bit exponent e, 12-bit mantissa m. e = 0: m / 256 samples; otherwise (1000 + m) * 2^(e-1) / 256. Fine steps close by, coarse far away. Minimum 1 sample. +2 byte LEFT signed, / 128 +3 byte RIGHT signed, / 128 +4 byte FB signed feedback, / 128 +5 byte FBMASK lines it feeds (bit n) +6 byte FBNEG lines it feeds negated +7 byte MODSRC bit 7 on, bits 0-4 op +8 byte MODDEPTH position + source * DEPTH * 2 samples +9-B reserved Feedback arrives one sample later. With masks and negations, four lines can form a feedback delay network (a reverb); see synth.asm. TOUCH ===== Up to ten touch points, 4 bytes each, at 80: x, y, flags (bit 0: down), reserved. A finger keeps its slot while it is down. Slot 0 is also the v3 pointer at 22-27. CAPTURE ======= The chip can copy what it played into RAM, once per frame, for oscilloscopes and graphics driven by sound. Channel n starts at 0B00 + n * 10. +00 byte SOURCE 00-1F operator output (waveform x envelope) 20-27 filter output 30 master left, 31 right +01 byte FORMAT bits per sample: 1, 2, 4, 8 or 16; anything else is off +02 word DEST RAM address +04 word COUNT samples, 1-4096 +06 byte STRIDE keep every Nth sample (0 counts as 1) +07 byte TRIGGER 0 none, 1 rising zero crossing, 2 falling; +4 auto-scale +08 byte GAIN / 16; 0 counts as 16 (x1). With auto-scale, the largest gain that keeps the window under 0.95. +09-0F reserved At the end of every frame (every 400 samples) the chip writes the channel's window to DEST, so the frame handler finds the previous frame's sound there. Without a trigger the window ends at the frame end. With one it starts at the latest crossing that still leaves a whole window, so a steady tone stands still on screen. The chip remembers 8192 samples per channel; COUNT * STRIDE above 4096 is cut to 4096. Formats: 16 is a signed word (7FFF = +1), low byte first; 8 a signed byte (7F = +1). 4, 2 and 1 are unsigned levels, 0 for -1 and the top value for +1, packed first sample in the high bits. Bytes that would land in 40-5F or 0400-0BFF are skipped. The capture is deterministic: the same program always sees the same bytes.